The present invention relates to a technology effectively applicable to a structural technology of wirings, bonding pads, and the like in a semiconductor integrated circuit device (or a semiconductor device).
In Japanese Unexamined Patent Publication No. 2011-114049 (Patent Document 1), there is disclosed a wiring layer configuration in which all the wiring layers except, for an aluminum-based pad layer are copper wirings in a memory type semiconductor integrated circuit device.
In Japanese Unexamined Patent Publication No.2011-129722 (Patent Document 2), there is disclosed a semiconductor integrated circuit device in which aluminum-based pads (including bonding pads and pads over a seal ring) are formed over a multilayer copper wiring.
In Japanese Unexamined Patent Publication No.2011-9581 (Patent Document 3) or its corresponding US Patent No. 2010-330799 A1 (Patent Document 4), there is disclosed a semiconductor integrated circuit device in which over the uppermost layer of copper embedded wirings, aluminum-based pads are formed without a relay metal member such as a tungsten plug interposed therebetween, and the bonding pads are coupled with bonding wires, respectively.
Japanese Unexamined Patent Publication No.2010-147267 (Patent Document 5) discloses the following: in a semiconductor integrated circuit device of a wafer level package system in which a rewiring is formed over an aluminum-based pad layer, the aluminum-based pad layer is used as the uppermost-layer metal wiring of copper damascene wirings, and furthermore, the same layer is used exclusively for pads.